This invention relates to a multiple channel microwave communications system and more particularly to a microwave communications system utilizing an improved diversity switch system which selects one of two data channels in which delays between the individual data channels are electronically equalized without the necessity of utilizing mechanical adjustment means such as coaxial cable lengths to match the on-line data or reference channel to that of the off-line or non-selected data channel.
In previous diversity systems precise data alignment had to be made so that the diversity switch could select from either source without introducing errors or losing data bits. For example, the bits from one channel had to be aligned in time with corresponding bits from another channel to permit selection of the optimum channel for the most error free transmission over a communications link. To achieve this uninterrupted operation, some form of absolute delay equalization had to be employed, particularly when modules having different delay characteristics were used. This was the case in a four-phase system in which delay differences of up to one-half a bit were common. In an eight-phase system, now widely used, compensation of delay differences of up to one bit were considered necessary in order to permit module replacement without readjusting for delay variations. This required the incorporation of discrete bit shifting in addition to a one-half bit delay achieved by inverting the clock to provide a 180.degree. phase shift in the timing circuit for each data line. Such adjustment to compensate for delays became difficult and inconvenient to perform.
Another common problem arises when the non-selected off-line channel of a diversity switch system fades. Errors are thereby created in the on-line data channel by changing the frequency of the timing or average clock for each channel. This makes the diversity switch useless under fading conditions.
Such fading also results in the off-line channel operating at an incorrect frequency and no alarm signal is given to inhibit its own clock output from reaching the clock averaging circuit, which results in incorrect timing of the average clock for both channels. When this condition occurs, the off-line channel creates errors in the on-line channel.